1. Field of the Invention
The present invention relates to a method for fabricating a capacitor for a semiconductor device, and more particularly, to a method for fabricating a cylinder-type capacitor for a semiconductor device.
2. Description of the Related Art
The performance characteristics of a memory cell such as a dynamic random access memory (DRAM) among semiconductor devices share an direct connection with the capacitance of the memory cell capacitor. For example, as the capacitance of the cell capacitor increases, the low voltage characteristics and soft error characteristics of the memory cell are improved.
As semiconductor devices continue to become more highly-integrated, the available area of a unit cell in which a capacitor is formed decreases. Thus, methods for increasing the capacitance of a capacitor within the limited area are necessary.
A number of techniques have been suggested for accomplishing capacitor integration. These include forming the capacitor dielectric layer into a thin film, using a material having a high dielectric constant as the dielectric layer, and increasing the effective area of a capacitor electrode by making a cylinder-type electrode or a fin-type electrode or by growing hemispherical grains (HSGs) on the surface of the electrode.
Hereinafter, referring to FIGS. 1 through 5, a conventional method for fabricating a cylinder-type capacitor for a semiconductor device will be described. Like reference numerals refer to like elements throughout the drawings.
Referring to FIG. 1, a first insulating layer 120 is formed on a semiconductor substrate 100 on which a conductive region 110 is formed. A first photoresist pattern 122 having a first opening A at the position corresponding to the conductive region 110 is formed on the first insulating layer 120.
Referring to FIG. 2, the exposed portion of the first insulating layer 120 is etched, using the first photoresist pattern 122 as a mask, and thereby forming a first insulating layer pattern 120a having a contact hole 125 for exposing the conductive region 110. After the first photoresist pattern 122 is removed, a first conductive layer 130 for filling the contact hole 125 is formed.
Referring to FIG. 3, the upper surface of a resultant structure shown in FIG. 2 is planarized to expose the upper surface of the first insulating layer pattern 120a, and thereby forming a contact plug 130a. A etch stop layer 140 and a second insulating layer 150 are formed in sequence on the surface of the top of the first insulating layer pattern 120a and the contact plug 130a. A second photoresist pattern 152 having a second opening B at a position above the contact plug 130a is formed on the second insulating layer 150.
Referring to FIG. 4, the second insulating layer 150 and the etch stop layer 140 are etched by using the second photoresist pattern 152 as a mask, and thereby forming a second insulating layer pattern 150a and an etch stop layer pattern 140a having a storage node hole 155 for exposing the surface of the top of the contact plug 130a. After the second photoresist pattern 152 is removed, a second conductive layer 160 is formed at a thickness such that the storage node hole 155 is not completely filled.
Referring to FIG. 5, the top of the second conductive layer 160 and the second insulating layer pattern 150a are removed to form a separated storage node 160a. A dielectric layer 180 and an upper electrode 190 are formed on the storage node 160a. 
According to the conventional method described above, in order to form a contact plug and a storage node, the photolithography process is performed twice, as described with reference to FIGS. 1 and 3. As described with reference to FIGS. 2 and 4, the process for forming a conductive layer is performed twice. The photolithography process is limited in that it requires the use of expensive exposure equipment having high resolution capabilities, and is a process that influences productivity due to high production cost. Also, since the polysilicon layer is formed by diffusion in the process for forming the conductive layer, the process takes a relatively long time to complete.
Thus, in the above conventional method for fabricating a cylinder-type capacitor of a semiconductor device, the number of processes is large, and the production cost is high.
To address the above limitations, it is an object of the present invention to provide a method for fabricating a cylinder-type capacitor for a semiconductor device, while reducing production cost and simplifying the process.
Accordingly, to achieve the above object, there is provided a method for fabricating a cylinder-type capacitor for a semiconductor device. The method includes the steps of forming in sequence a first insulating layer, a first etch stop layer, a second insulating layer, and a second etch stop layer on a semiconductor substrate including a conductive region, forming a second etch stop layer pattern, a second insulating layer pattern, and a first etch stop layer pattern by etching a part of the second etch stop layer, the second insulating layer, and the first etch stop layer so that a storage node hole for exposing the surface of a part of the first insulating layer may be formed, forming a spacer on an inner wall of the storage node hole, forming a first insulating layer pattern by etching the first insulating layer exposed using the second etch stop layer pattern and the spacer as a mask so that a node contact hole for exposing the conductive region may be formed, removing the second etch stop layer pattern and the spacer, forming a lower electrode on exposed surfaces of the storage node hole and the node contact hole, and forming a dielectric layer and an upper electrode on the lower electrode.
The conductive region may be an active region on the surface of the semiconductor substrate, or a contact pad on the top of the semiconductor substrate.
The method further includes the step of forming a contact pad self-aligned by two neighboring gate electrodes formed on the semiconductor substrate, and the conductive region may be the contact pad. Here, the step of forming a contact pad includes the steps of forming an interdielectric layer which fills a space between the two gate electrodes, forming a contact hole for exposing the surface of the semiconductor substrate between the two neighboring gate electrodes by patterning the interdielectric layer, and filling a conductive material in the contact hole. The gate electrodes may be formed of the structure of a polycide in which a silicide layer is formed on a polysilicon layer. The interdielectric layer may be formed of a boron phosphorus silicate glass (BPSG) layer, a spin on glass (SOG) layer, an undoped silicate glass (USG) layer, a silicon oxide layer formed by using a high density plasma-chemical vapor deposition (HDP-CVD) method, or a tetraethylorthosilicate (TEOS) layer formed by using a plasma enhanced-CVD (PE-CVD) method.
The method further includes the steps of forming a silicon oxide layer on the second etch stop layer, forming a silicon oxide layer pattern by etching a part of the silicon oxide layer so that the storage node hole may be formed, and removing the silicon oxide layer pattern during the formation of the node contact hole. The silicon oxide layer is preferably a silicon oxide layer formed by using a PE-CVD method, or a high temperature oxide layer.
The first insulating layer may be a silicon oxide layer formed by a HDP-CVD method, and the second insulating layer may be a TEOS layer formed by a PE-CVD method. The first etch stop layer and the second etch stop layer may be silicon nitride layers, respectively, formed by a low pressure-CVD (LP-CVD) method.
The thickness of the first insulating layer may be between 8000 and 12000 xc3x85, and the thickness of the second insulating layer may be between 5000 and 20000 xc3x85, and the thickness of the first etch stop layer and the second etch stop layer may be between 300 and 500 xc3x85, respectively.
The step of forming a spacer includes the steps of forming a third insulating layer to have a thickness with which the storage node hole may not be completely filled, and etching-back the third insulating layer. The third insulating layer may be a silicon nitride layer or a silicon oxynitride layer formed by a PE-CVD method.
The step of removing the second etch stop layer pattern and the spacer is performed by removing the spacer after the removal of the second etch stop layer pattern, or by simultaneously removing the second etch stop layer pattern and the spacer.
The step of removing the second etch stop layer pattern and the spacer is performed by a wet etching method using a mixed solution of hydrogen peroxide, water (H2O), and hydrofluoric acid (HF).
The step of forming a lower electrode includes the steps of forming a conductive layer having the thickness with which the storage node hole and the node contact hole may not be completely filled, on the entire surface of a resultant on which the node contact hole is formed, and forming a plurality of separated storage nodes by removing the top of the conductive layer and the second insulating layer pattern. The conductive layer may be formed of a polysilicon layer by diffusion. The step of forming a plurality of plurality storage nodes includes the steps of forming an oxide layer which fills the storage node hole and the node contact hole, on the conductive layer, removing a part of the oxide layer and the top of the conductive layer so that the second insulating layer pattern may be exposed, and removing the oxide layer which fills the storage node hole and the node contact hole, and the second insulating layer pattern by a wet-etching method. Preferably, the oxide layer is formed of a USG layer, a BPSG layer, a double layer of a silicon oxide layer and a USG layer, or a double layer of a silicon oxide layer and a BPSG layer.
The step of forming a lower electrode may further includes the step of forming hemispherical grains (HSGs) on the surface of the storage node.
The dielectric layer may be formed of a Al2O3 layer, a Ta2O5 layer, a SrTiO3(STO) layer, (Ba, Sr) TiO3(BST) layer, a PbTiO3 layer, Pb(Zr, Ti)O3(PZT) layer, a SrBi2Ta2O9(SBT) layer, (Pb,La)(Zr,Ti)O3 layer, or BaTiO3(BTO) layer. Alternatively, the dielectric layer may be formed of a triple layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, or a double layer of a silicon nitride layer and a silicon oxide layer.
The upper electrode may be formed by using a polysilicon layer by diffusion.
According to the present invention, a photolithography process and a process for forming a conductive layer are each performed once, respectively. Thus, the overall fabrication process is simplified, and productivity is improved and production cost reduced.